\doxysubsubsubsection{RCCEx ADC Clock Source }
\hypertarget{group___r_c_c_ex___a_d_c___clock___source}{}\label{group___r_c_c_ex___a_d_c___clock___source}\index{RCCEx ADC Clock Source@{RCCEx ADC Clock Source}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{group___r_c_c_ex___a_d_c___clock___source_gaac8951308d2abaed9daa4f596d092dd5}\label{group___r_c_c_ex___a_d_c___clock___source_gaac8951308d2abaed9daa4f596d092dd5} 
\#define {\bfseries RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+PLL2}~(0x00000000U)
\item 
\Hypertarget{group___r_c_c_ex___a_d_c___clock___source_gad05173624318bceb82c54ccc3698dbf8}\label{group___r_c_c_ex___a_d_c___clock___source_gad05173624318bceb82c54ccc3698dbf8} 
\#define {\bfseries RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+PLL3}~RCC\+\_\+\+SRDCCIPR\+\_\+\+ADCSEL\+\_\+0
\item 
\Hypertarget{group___r_c_c_ex___a_d_c___clock___source_ga1ba73db5320d6e04b2cc4e3e9bfa6553}\label{group___r_c_c_ex___a_d_c___clock___source_ga1ba73db5320d6e04b2cc4e3e9bfa6553} 
\#define {\bfseries RCC\+\_\+\+ADCCLKSOURCE\+\_\+\+CLKP}~RCC\+\_\+\+SRDCCIPR\+\_\+\+ADCSEL\+\_\+1
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
